Scaling down of metal-oxide-semiconductor field effect transistors (MOSFETs) has enabled continued improvement in speed, performance, functional density, and production cost. One way to further improve MOSFET performance is through selective application of stress to a channel region of the transistor. Stress distorts (i.e., strains) semiconductor crystal lattice, and distortion, in turn, affects band alignment and lattice structure of a semiconductor.
To enhance the performance of metal-oxide-semiconductor (MOS) devices, stress may be introduced in the channel regions of the MOS devices to improve carrier mobility. Generally, it is desirable to induce a tensile stress in the channel region of an n-type MOS (“NMOS”) device in a source-to-drain direction, and to induce a compressive stress in the channel region of a p-type MOS (“PMOS”) device in a source-to-drain direction.
A commonly used method for applying compressive stress to the channel regions of PMOS devices is by growing SiGe stressors in the source and drain regions. Such a method typically includes the steps of forming a gate stack on a silicon substrate, forming spacers on sidewalls of a gate stack, forming recess in the silicon substrate and adjacent to the gate spacer, and epitaxially growing SiGe stressors in the recess. An annealing is then performed. Since SiGe has a greater lattice constant than silicon, it expands after annealing and applies a compressive stress to the channel region of the respective MOS device, which is located between a source SiGe stressor and a drain SiGe stressor.